1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a liquid crystal display panel, a data driver, an LCD device using the same, and a driving method for an LCD device.
2. Discussion of the Related Art
With the rise of an information society the demand for display devices has increased. To meet the demand, various types of display devices including liquid crystal display (LCD) devices, plasma display panels (PDP), electro luminescent devices (ELD), and vacuum fluorescent displays (VFD). Some of these devices are currently in use as display devices.
Among the various types of display devices, the LCD device has been widely used because of advantages including excellent image quality, light weight, compact profile, and low power consumption. Accordingly, the LCD device has been in various applications including as a monitor for a portable apparatuses and as a display panel for televisions.
In the typical LCD device, data are respectively supplied to a matrix of pixels, and a desired image can be displayed by controlling the light transmittances of the pixels.
FIG. 1 is a block diagram of a related art LCD device. FIG. 2 is a circuit diagram illustrating a liquid crystal display panel of FIG. 1, and FIG. 3 is a block diagram illustrating a data driver of the liquid crystal display panel of FIG. 1.
Referring to FIG. 1, the related art LCD device includes a liquid crystal display panel 9, a gate driver 3, a gamma generator 7, a data driver 5, a common voltage generator 8, and a timing controller 1. The liquid crystal display panel 9 includes a plurality of pixels arranged in a matrix. The gate driver 3 supplies a scan signal to the liquid crystal display panel 9. The data driver 5 supplies a data voltage based on the gamma voltage corresponding to R, G and B data signals forming an image to the liquid crystal display panel 9. The common voltage generator 8 generates a common voltage Vcom to be applied to the liquid crystal display panel 9. The timing controller 1 generates a control signal for controlling the gate driver 3 and the data driver 5.
The liquid crystal display panel 9 may have various structures depending upon the mode of operation of the liquid crystal display panel 9. The liquid crystal display panel of FIG. 2 operates in an in-plane switching (IPS) mode.
Referring to FIG. 2, a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm are arranged on the liquid crystal display panel 9 such that the plurality of gate lines G1 to Gn cross the plurality of data lines D1 to Dm. A plurality of pixels P is defined by crossings of the plurality of gate lines G1 to Gn with the plurality of data lines D1 to Dm. Each pixel P includes a thin film transistor (TFT) connected to a gate line G1 to Gn and the data line D1 to Dm, and a pixel electrode (not shown) connected to the TFT. Although not shown, the pixel P also includes a common electrode branched from the common line VL1 to VLn.
A data voltage is applied to the pixel electrode, and a common voltage Vcom is applied to the common electrode resulting in a potential difference (i.e., voltage difference) between the data voltage and the common voltage Vcom applied to the pixel electrode and the common electrode. Molecules of a liquid crystal layer existing between the pixel electrode and the common electrode are driven by means of the potential difference. Liquid crystal cells represented as capacitors (Clc) are formed by the liquid crystal molecules of each pixel. Although not shown, a storage capacitor for maintaining the data voltage applied to the pixel for one frame (or one frame period) may be formed between the gate line G1 to Gn and the pixel electrode.
The timing controller 1 generates a control signal for driving the liquid crystal display panel 9 using image data and synchronization signal input from an external source such as an external video card. The control signal includes a first control signal that controls the gate driver 3, and a second control signal that controls the data driver 5. The first control signal includes a gate shift clock (GSC), a gate start pulse (GSP), and a gate output enable (GOE) signal. The second control signal includes source shift clock (SSC), source start pulse (SSP), source output enable (SOE) signal, and a polarity control (POL) signal.
The gate driver 3 sequentially supplies the scan signals to the respective gate lines G1 to Gn in response to the first control signal supplied from the timing controller 1. Accordingly, each of the respective gate lines G1 to Gn of the liquid crystal display panel 9 is activated in sequence. By activation it is meant that the TFTs connected to a respective gate lines G1 to Gn are turned on by the scan signal. When the TFTs are turned on, the data voltage supplied from the data driver 5 is supplied to the pixel electrode via the TFT connected to the activated gate line.
Referring to FIG. 3, the data driver 5 includes a data latch unit 13, a shift register 12, a line latch unit 14, a digital to analog (DA) converter 16, and an output buffer unit 17.
The data latch unit 13 latches n-bit R, G and B data signals supplied from the timing controller 1 in units of pixels. The shift register 12 sequentially generates the latch enable signals that control the line latch unit 14 to latch the R, G and B data signals latched in the data latch unit 13 in synchronization with the SSC signal, when the SSP signal is applied to the shift register 12. In response to the latch enable signals that are sequentially generated at the shift register 12, the R, G and B data signals latched in the data latch unit 13 are latched in the line latch unit 14 in sequence. For example, the R, G and B data signals are simultaneously latched in the line latch unit 14 in response to a first latch enable signal output from the shift register 12. Similarly, the R, G and B data signals are simultaneously latched in the line latch unit 14 in response to a second latch enable signal output from the shift register 12. Through a sequence of such operations, the line latch unit 14 latches a volume of data corresponding to one horizontal display line.
The line latch unit 14 can latch the data signals corresponding to a preset number of channels. As illustrated in FIG. 3, the line latch 14 can latch the data signals corresponding to 192 channels OUT1 to OUT192.
For example, when the number of the data lines of the liquid crystal display panel 9 is 576, the number of channels of the data driver 5 corresponding to the respective data lines should also be 576. However, since the number of channels for a data driver IC is 192 in the data driver 5 of FIG. 3, the data driver 5 can provide 576 channels by including three data driver ICs each having 192 channels.
The DA converter 16 converts the R, G and B data signals latched at the line latch unit 14 into R, G and B data voltages corresponding to a gamma voltage supplied from the gamma generator 7. The DA converter 16 may generate the R, G and B data voltages using one of a positive polarity gamma voltage and a negative polarity gamma voltage supplied from the gamma generator 7.
The output buffer unit 17 outputs the R, G and B data voltages to the respective channels OUT1 to OUT192 in response to the SOE signal. Each channel is connected to a respective data line of the liquid crystal display panel 9.
By using the data driver of the above-described configuration, the related art LCD device may alternately supply a data voltage based on the positive polarity gamma voltage and the data voltage based on the negative polarity gamma voltage to operate the related art LCD in an inversion mode.
However, the related art LCD device includes a plurality of common lines corresponding to the number of gate lines in the liquid crystal display panel 9. Because a pixel includes one or more common lines as well as the gate and data lines, the overall aperture ratio of the related art LCD device is decreased.
In addition, the related art LCD device has an inherent limitation affecting the voltage difference between the voltages for driving liquid crystals, i.e., the voltage difference between the data voltage and the common voltage. Because the common voltage is typically set to half of the data voltage, the potential difference between the common voltage and the data voltage is limited and increasing the data voltage produces only a limited increase in the potential difference. Accordingly, a limit is encountered when attempting to increase the potential difference to obtain a high brightness level to enhance the image quality of the display.
Moreover, the limitation on the potential difference between the data voltage and the common voltage limits improving a response speed of the liquid crystal by operating the display with an increased potential difference
Furthermore, because the related art LCD device requires a common line and circuitry for generating the common voltage to be supplied to the common line, problems including a complicated fabrication process, high fabrication cost, and low aperture ratio are created.